ASIC/FPGA Engineer - RTL Design in VHDL
Your main tasks and responsibilities will include:
- Decomposition of requirements into an architecture design and document the chosen design whilst describing any trade-offs performed.
- Detailed RTL design in VHDL.
- Verification of the RTL design and documenting the verification that was performed.
- Gate level implementation of the design including synthesis, placement and static timing analysis.
- Support integration of the ASIC/FPGA into the target hardware.
- Ensure that all ASIC/FPGA designs are developed in accordance with the company design process.
- Support customer design reviews.
- Experienced in the complete design flow from requirements to design acceptance.
- Experienced in FPGA technologies and their tools including Xilinx ISE and Microsemi Libero.
- Experienced in VHDL simulation tools in particular Mentor Graphics Questa.
- Experienced in synthesis and STA tools ideally those from Synopsys.
- Good analytical skills and methodical approach to problem resolution and investigations.
- Good communication skills and able to thrive in a team environment.
- Ability to present technical data in a clear and concise manner.
- Experience of the Linux operating system would be beneficial.
- Knowledge of Scripting languages including TCL and PERL would be beneficial.
- Educated to degree level in Electronic Engineering or related discipline
If you are interested in discussing this role, please apply and we will schedule a confidential call.
Capital International Staffing Ltd is acting as an Employment Business in relation to this vacancy.